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authorJozanLeClerc <>2022-05-22 15:00:14 +0000
committerJozanLeClerc <>2022-05-22 15:00:14 +0000
commit427859267528358fd0d376fd4db9a6308e44f2ab (patch)
tree9b9fe8ef1120038cf9ae74f9a4da5a38b6050502 /src/c_cpu.S
parenttest (diff)
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Added
FossilOrigin-Name: 7326c5d114e989120133de3424d736788368285d
Diffstat (limited to 'src/c_cpu.S')
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diff --git a/src/c_cpu.S b/src/c_cpu.S
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+/*
+ * ========================
+ * ===== ===============
+ * ====== ================
+ * ====== ================
+ * ====== ==== ==== ==
+ * ====== === == = =
+ * ====== === = == =
+ * = === === = == ====
+ * = === === = == = =
+ * == ===== ==== ==
+ * ========================
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2022 Joe
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the organization nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY JOE ''AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL JOE BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * asm-cgi-example: src/c_cpu.S
+ * Sun May 22 16:51:35 CEST 2022
+ * Joe
+ */
+
+.text
+.globl c_cpu
+
+c_cpu:
+fork_model:
+ xorq %rdi, %rdi
+ xorq %rsi, %rsi
+ xorq %rax, %rax
+ movb $0x2, %al /* SYS_fork */
+ syscall
+ cmp $0x0, %rax
+ jl err
+ je exec_model
+ jg wait_model
+
+fork_ncpu:
+ xorq %rdi, %rdi
+ xorq %rsi, %rsi
+ xorq %rax, %rax
+ movb $0x2, %al /* SYS_fork */
+ syscall
+ cmp $0x0, %rax
+ jl err
+ je exec_ncpu
+ jg wait_ncpu
+
+fork_lscpu:
+ xorq %rdi, %rdi
+ xorq %rsi, %rsi
+ xorq %rax, %rax
+ movb $0x2, %al /* SYS_fork */
+ syscall
+ cmp $0x0, %rax
+ jl err
+ je exec_lscpu
+ jg wait_lscpu
+
+exec_model:
+ xorq %rax, %rax
+ pushq %rbp
+ movq %rsp, %rbp
+ movq $sysctl, -32(%rbp)
+ movq $model, -24(%rbp)
+ movq $0x0, -16(%rbp)
+ movq -32(%rbp), %rdi
+ leaq -32(%rbp), %rsi
+ xorq %rdx, %rdx
+ movq $0x3b, %rax /* SYS_execve */
+ syscall
+ popq %rbp
+ retq
+
+exec_ncpu:
+ xorq %rdi, %rdi
+ xorq %rsi, %rsi
+ xorq %rax, %rax
+ pushq %rbp
+ movq %rsp, %rbp
+ movq $sysctl, -32(%rbp)
+ movq $ncpu, -24(%rbp)
+ movq $0x0, -16(%rbp)
+ movq -32(%rbp), %rdi
+ leaq -32(%rbp), %rsi
+ xorq %rdx, %rdx
+ movq $0x3b, %rax /* SYS_execve */
+ syscall
+ popq %rbp
+
+exec_lscpu:
+ xorq %rdi, %rdi
+ xorq %rsi, %rsi
+ xorq %rax, %rax
+ pushq %rbp
+ movq %rsp, %rbp
+ movq $lscpu, -24(%rbp)
+ movq $0x0, -16(%rbp)
+ movq -24(%rbp), %rdi
+ leaq -24(%rbp), %rsi
+ xorq %rdx, %rdx
+ movq $0x3b, %rax /* SYS_execve */
+ syscall
+ popq %rbp
+
+wait_model:
+ movq %rax, %rdi
+ xorq %rsi, %rsi
+ xorq %rdx, %rdx
+ xorq %rcx, %rcx
+ xorq %rax, %rax
+ movb $0x7, %al /* sys_wait4 */
+ syscall
+ jmp fork_ncpu
+
+wait_ncpu:
+ movq %rax, %rdi
+ xorq %rsi, %rsi
+ xorq %rdx, %rdx
+ xorq %rcx, %rcx
+ xorq %rax, %rax
+ movb $0x7, %al /* sys_wait4 */
+ syscall
+ jmp fork_lscpu
+
+wait_lscpu:
+ movq %rax, %rdi
+ xorq %rsi, %rsi
+ xorq %rdx, %rdx
+ xorq %rcx, %rcx
+ xorq %rax, %rax
+ movb $0x7, %al /* sys_wait4 */
+ syscall
+ retq
+
+err:
+ xorq %rdi, %rdi
+ xorq %rax, %rax
+ movb $0x1, %dil
+ movb $0x1, %al
+ syscall
+
+.data
+# sysctl hw.model\n\t\t\tsysctl hw.ncpu\n\t\t\tlscpu
+ sysctl: .asciz "/sbin/sysctl"
+ lscpu: .asciz "/usr/local/bin/lscpu"
+ model: .asciz "hw.model"
+ ncpu: .asciz "hw.ncpu"